Abstract :

This Paper Presents A Hybrid Fault-tolerant 64×16 Random Access Memory (RAM) Subsystem Designed To Mitigate Both Transient And Permanent Faults Using A Combination Of Error Detection Code (EDC), Error Correction Code (ECC), And Built-In Self-Test (BIST) Techniques. Developed In Verilog HDL And Verified With A System Verilog-based Environment, The Architecture Integrates Multiple Resilience Strategies To Enhance Memory Reliability In Safety-critical And Highdependability Applications. The ECC Module Implements A Hamming-based SEC-DED (Single Error Correction – Double Error Detection) Scheme, Encoding 16-bit Input Data With Five Parity Bits To Generate A 21-bit Output, Enabling Real-time Correction Of Single-bit Errors And Detection Of Double-bit Faults. The EDC Mechanisms Provide Additional Lightweight Detection During Normal Operation, Offering Fast Identification Of Error Patterns Before Correction Or Isolation. The BIST Controller Autonomously Initiates Test Routines By Writing Known Patterns To Memory, Reading Them Back, And Comparing The Results To Identify Permanent Faults Without Requiring External Testing Hardware. The Top-level Architecture Seamlessly Switches Between Normal Operation And Self-test Modes, Ensuring Uninterrupted Functionality. Extensive Simulation Using Randomized And Fault-injection Scenarios Confirms The Designs Robustness, Demonstrating Reliable Error Detection And Correction Across Varying Fault Conditions. This Hybrid Solution Provides An Efficient And Scalable Framework For Fault Mitigation In Modern Memory Subsystems.

Published:

22-7-2025

Issue:

Vol. 25 No. 7 (2025)

Page Nos:

764 - 768

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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