ISSN No:2250-3676
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Scholarly Peer Reviewed and Fully Referred Open Access Multidisciplinary Monthly Research Journal


    A LOW-POWER HIGH-SPEED ACCURACYCONTROLLABLE APPROXIMATE MULTIPLIER DESIGN

    Adavathu Rajitha,Mr. DEVISINGH

    Author

    ID: 1487

    DOI:

    Abstract :

    This Paper Presents An Accuracy-controllable Multiplier That Generates Its Final Product Using A Carry-maskable Adder. The Scheme Can Dynamically Adjust The Carry Propagation Length To Meet Accuracy Requirements. The Approximate Multiplier Consists Of An Approximate Tree Compressor (ATC) And A Carry-maskable Adder (CMA), Which Compress Partial Products Powerefficiently And Provide Accuracy Scalability Using A Simple Carry-masking Technique. The 8x8 Approximate Multiplier Is Implemented In Verilog HDL, Dividing The Design Into Four Stages: Partial Product Generation, Hierarchical Tree Compression, OR-based Summation Of Compensation Vectors, And A Final Addition Using A Hybrid Adder. The Implementation Balances Accuracy, Speed, And Power, Making It Suitable For Energy-efficient Approximate Computing In Image Processing, Machine Learning, And Embedded Signal Processing Applications. Index Terms: - Approximate Multiplier, Accuracy-controllable Multiplier, Carry-maskable Adder (CMA), Approximate Tree Compressor (ATC), Verilog HDL, Hybrid Adder, Truncated OR Logic, Ripple-carry Adder.

    Published:

    26-7-2025

    Issue:

    Vol. 25 No. 7 (2025)


    Page Nos:

    812-818


    Section:

    Articles

    License:

    This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

    How to Cite

    Adavathu Rajitha,Mr. DEVISINGH, A LOW-POWER HIGH-SPEED ACCURACYCONTROLLABLE APPROXIMATE MULTIPLIER DESIGN , 2025, International Journal of Engineering Sciences and Advanced Technology, 25(7), Page 812-818, ISSN No: 2250-3676.

    DOI: