Abstract :

The Authors Propose A Sustainable And FPGAimplementable Approach To Error Correction In Deeply Scaled Memories, SFaultMap. The Novel Fault Map Architecture Optimizes Operational And Embodied Energy, Achieving Lower Energy Consumption Over A Five-year Lifetime Under Moderate To High Fault Rates. SFaultMap+ Enhances Fault Tolerance By Shifting Focus From Error Correction Overhead To System-level Sustainability And Hardware Efficiency. The Modular Verilog Design Allows Real-time Fault Masking, Scalable Support For Continuation Segments, Fault Threshold Tuning, And Fast Decoding. The Architecture Has Been Validated Through Functional Simulation And Synthesis Using Xilinx Vivado. Index Terms: - SFaultMap, Memory Fault Tolerance, Fpga, Energy-efficient Design, Error Correction, Continuation Segment

Published:

26-7-2025

Issue:

Vol. 25 No. 7 (2025)

Page Nos:

819-828

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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