Abstract :

Ternary Logic, A Type Of Multi-valued Logic (MVL), Offers Notable Advantages Over Traditional Binary Logic In Terms Of Circuit Density, Power Efficiency, And Computational Performance. This Paper Proposes A Novel Design For A Ternary Full Adder (TFA), Which Is Developed Using An Optimized Ternary Half Adder (proposed THA). The TFA Circuits Are Implemented Using Carbon Nanotube Fieldeffect Transistors (CNTFETs), Which Are Highly Suitable For MVL Systems Due To Their Ability To Support Multiple Threshold Voltages. The Proposed THA Design Plays A Key Role In Improving The Overall Performance Of The TFA By Significantly Reducing Transistor Count, Power Consumption, And Propagation Delay. The Entire System Is Modeled And Simulated Using HSPICE With Stanford’s 32nm CNTFET Technology At A Supply Voltage Of 0.9V. Simulation Results Confirm The Efficiency Of The Proposed Circuits, Showcasing Improvements In Energy Consumption, Speed, And Accuracy. These Advancements Make The Design A Promising Solution For Future Nanoscale Arithmetic Operations And Energyefficient Computing Platforms. Keywords—Ternary Half Adder, Ternary Full Adder, HSPICE

Published:

24-11-2025

Issue:

Vol. 25 No. 11 (2025)

Page Nos:

236-243

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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