Abstract :

Embedded Systems Used In Safety-critical Applications Demand The Highest Level Of Reliability. External Monitor Timers Are Used For The Automated Handling And Recovery Of Errors Related To Running Time In These Systems. Many Of The External Watchdog Timers Available Use Additional Circuits To Change Their Timeouts And Provide Only Minimal Functionality Features. This Paper Describes The Architecture And Design Of An Improved Configurable Watchdog Timer Which Can Be Used In Critical Security Applications. Many Mechanisms For Detecting Faults Are Integrated Into The Firewall, Contributing To Its Robustness. The Features And Operations Are Very Common And Can Be Used To Track The Operations Of Any Real-time Processorbased Device. This Paper Also Addresses The Proposed Watchdog Timer In A Field Programmable Gate Array (FPGA) Implementation. This Makes Fast Adaptation Of The Design To Various Applications, While Reducing Overall Device Costs. First, By Analyzing The Simulation Model, The Implementation Of The Proposed Watchdog Timer To Detect And Respond To Faults Is Studied. The Design Is Validated In Real- Time Hardware By Injecting Faults Through The Software During The Execution Of The Processor And Drawing Conclusions. Keywords: Watchdog Timer, FPGA Implementation, Safety-Critical Systems, Embedded Systems, Fault Detection, Real-Time Monitoring, Configurable Architecture, Hardware Validation.

Published:

03-12-2025

Issue:

Vol. 25 No. 12 (2025)

Page Nos:

44-50

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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