Abstract :

Multipliers Are Essential Computational Units Widely Utilized In Digital Signal Processing (DSP), Image Processing, Cryptography, And High-performance Embedded Architectures, Where Speed, Power Efficiency, And Silicon Area Utilization Are Critical Design Requirements. Conventional Multiplier Architectures Typically Encounter Challenges In Balancing Trade-offs Between Operational Speed, Hardware Complexity, And Power Dissipation. This Work Presents The Design And Performance Evaluation Of An 8×8-bit Multiplier Based On The Additive Multiply Module (AMM) Architecture, Which Enhances Efficiency By Reducing Partial Product Generation And Simplifying Accumulation Logic. The Proposed AMM-based Multiplier Is Analysed With Respect To Key Performance Metrics Including Delay, Power Consumption, Area Utilization, And Throughput, Using Both Behavioural And Structural Modelling In Hardware Description Language (HDL). Comparative Analysis With Traditional Architectures Such As Array Multipliers And Booth Multipliers Demonstrates That The AMM Design Achieves Notable Improvements, Particularly In Low-power And High-speed Operational Environments. Simulation Results Confirm Substantial Performance Gains, Validating The AMM Architecture As A Promising Candidate For Scalable Integration Into Larger Arithmetic Processing Units In Modern VLSI Systems. Keywords: AMM, Conventional Architecture, High-speed, Performance Gains, Multiplier.

Published:

11-12-2025

Issue:

Vol. 25 No. 12 (2025)

Page Nos:

191-198

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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