Abstract :

In The Realm Of Digital Signal Processing, The Design Of Multiply-Accumulate (MAC) Units Plays A Pivotal Role In Achieving High-performance Computations. The MAC Design Finds Application In Various Fields Such As Digital Signal Processing, Communications, And Artificial Intelligence, Where MAC Operations Are Fundamental For Efficient Computation Of Convolutional Neural Networks, Digital Filters, And Other Signal Processing Tasks. Currently, MAC Units Commonly Rely On Separate Adders And Multipliers, Leading To Increased Hardware Complexity And Power Consumption. The Existing Systems Often Struggle To Strike A Balance Between Speed And Resource Utilization. Traditional MAC Designs Entail Redundant Hardware Due To The Independent Implementation Of Adders And Multipliers. Separate Adders And Multipliers Contribute To Higher Power Consumption, Limiting Energy Efficiency. The Existing Systems May Face Scalability Challenges, Especially When Aiming For High-performance Computing, Due To Their Architecture. This Work Introduces A Novel Approach To MAC Unit Design By Employing Unified Adders And Multipliers, Aiming To Enhance Both Speed And Resource Utilization. The Proposed Method Integrates Unified Adders And Multipliers, Optimizing The MAC Unit For Improved Speed And Efficiency. By Leveraging A Unified Architecture, The Design Minimizes Redundancy, Enhances Resource Utilization, And Reduces Power Consumption Keywords: MAC Unit, Redundancy, Highperformance Computing, Enhances Resource Utilization, Unified Architecture.

Published:

11-12-2025

Issue:

Vol. 25 No. 12 (2025)

Page Nos:

199-206

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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