Abstract :

As Semiconductor Technology Progresses, The Need For Energy-efficient Digital Circuits Continues To Rise, Especially In Applications Such As Portable Devices And Data Centers. F In FET (Fin Field Effect Transistor) Technology Has Emerged As A Revolutionary Advancement, Offering Enhanced Control Over Short-channel Effects, Thereby Minimizing Power Leakage And Improving Overall Efficiency. This Paper Explores The Design AndsimulationofcountersutilizingFinFETbasedDFlip-Flopsatthe10nm Technology Node, Implemented In LT- Spice, A Popular Circuit Simulation Tool. Compared To Conventional CMOS Designs, F In FET-based Counters Exhibit A Remarkable Reduction In Power Consumption And Noise, With Improvements Of 57.13% And 46.02%, Respectively. Additionally, Asynchronous And Johnson Counters Implemented With F In FET Technology Outperform Their CMOS Counterparts In Terms Of Speed And Reliability. These Findings Affirm That F In FET Technology Is Available Solution For Achieving High-speed, Low-power Digital Circuits, Making It An Ideal Choice For Future Semiconductor Designs. Keywords: FinFETTechnology, CMOS Limitations, Short-Channel Effects, D Flip-Flop Design, LT- Spice Tool, Power Efficiency, Noise Reduction, Semiconductor Advancement.

Published:

03-01-2026

Issue:

Vol. 26 No. 01 (2026)

Page Nos:

1-7

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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