ISSN No:2250-3676 ----- Crossref DOI Prefix: 10.64771
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(Peer Reviewed, Referred & Indexed Journal)


    Implementation And Analysis On FIFO Using FPGA

    A Roopa Sree,E Bala Krishna,Y. L. Ajay Kumar

    Author

    ID: 1945

    DOI:

    Abstract :

    Several Regions Across India Are Currently Experiencing Significant Energy Shortages. This Study Investigates The Implementation Of An Optimized First-In-First- Out (FIFO) Mechanism Using FieldProgrammable Gate Array (FPGA) Technology To Enhance Environmentally Sustainable Transmission Systems. FIFO, Which Manages And Processes Items Or Data In The Order They Are Received, Mirrors The Intuitive Operation Of Real Life Queues And Lines. The Proposed Design Employs The Genesys Board As The FPGA Hardware, Which Offers High Performance, Gigabit Ethernet Connectivity, And Design Flexibility, Making It Suitable For Highly Complex Applications. The Integration Of This Optimized FIFO Mechanism On The Genesys FPGA Board Demonstrates Potential Improvements In The Efficiency And Sustainability Of Energy Transmission Systems, Addressing Current Energy Shortfalls Effectively. Key Terms— Xilinx, FPGA, Energy Effieciency, Viva Do, First In First Out (FIFO).

    Published:

    03-01-2026

    Issue:

    Vol. 26 No. 01 (2026)


    Page Nos:

    8-13


    Section:

    Articles

    License:

    This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

    How to Cite

    A Roopa Sree,E Bala Krishna,Y. L. Ajay Kumar, Implementation and Analysis on FIFO using FPGA , 2026, International Journal of Engineering Sciences and Advanced Technology, 26(01), Page 8-13, ISSN No: 2250-3676.

    DOI: