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DESIGN AND SIMULATION OF 32-BIT ARITHMETIC LOGIC UNIT DEVELOPMENT USING VERILOG

M.VINEETHA,DR.CH.VENUGOPALREDDY, T. KALA VYSHNAVI, P.V. ANEESHA, J. HARI PRIYA

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ID: 2049

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Abstract :

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Published:

21-2-2026

Issue:

Vol. 26 No. 2 (2026)

Page Nos:

104-110

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

How to Cite

M.VINEETHA,DR.CH.VENUGOPALREDDY, T. KALA VYSHNAVI, P.V. ANEESHA, J. HARI PRIYA, DESIGN AND SIMULATION OF 32-BIT ARITHMETIC LOGIC UNIT DEVELOPMENT USING VERILOG , 2026, International Journal of Engineering Sciences and Advanced Technology, 26(2), Page 104-110, ISSN No: 2250-3676.

DOI:

ISSN No:2250-3676 ----- Crossref DOI Prefix: 10.64771 ----- Impact Factor: 9.625