HPVA-AES: Hybrid Pipelined VLSI Architecture For High-Throughput AES-128 Cryptography Using Optimised Parallel Encryption And DecryptionID: 3620 Abstract : |
Published:23-7-2026 Issue:Vol. 26 No. 7 (2026) Page Nos:1174 - 1182 Section:Articles License:This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License. How to CiteKongari Anil Kumar ,Mrs.Jonnagoni Sumalatha, HPVA-AES: Hybrid Pipelined VLSI Architecture for High-Throughput AES-128 Cryptography Using Optimised Parallel Encryption and Decryption , 2026, International Journal of Engineering Sciences and Advanced Technology, 26(7), Page 1174 - 1182, ISSN No: 2250-3676. |