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Mixed-Logic Hierarchical Predecode Decoders For Area- And PowerEfficient Address Decoding

Chiluveru Archana ,Jeedimadla Venkatesham

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ID: 3622

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Abstract :

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Published:

23-7-2026

Issue:

Vol. 26 No. 7 (2026)

Page Nos:

1190 - 1197

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

How to Cite

Chiluveru Archana ,Jeedimadla Venkatesham, Mixed-Logic Hierarchical Predecode Decoders for Area- and PowerEfficient Address Decoding , 2026, International Journal of Engineering Sciences and Advanced Technology, 26(7), Page 1190 - 1197, ISSN No: 2250-3676.

DOI:

ISSN No:2250-3676 ----- Crossref DOI Prefix: 10.64771 ----- Impact Factor: 9.625