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A True Single-Phase Clock Hybrid D Flip-Flop For Low-Power CMOS Sequential Logic

Aella Madhavi ,Mr.Jeedimadla Venkatesham

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ID: 3623

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Abstract :

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Published:

23-7-2026

Issue:

Vol. 26 No. 7 (2026)

Page Nos:

1198 - 1204

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

How to Cite

Aella Madhavi ,Mr.Jeedimadla Venkatesham, A True Single-Phase Clock Hybrid D Flip-Flop for Low-Power CMOS Sequential Logic , 2026, International Journal of Engineering Sciences and Advanced Technology, 26(7), Page 1198 - 1204, ISSN No: 2250-3676.

DOI:

ISSN No:2250-3676 ----- Crossref DOI Prefix: 10.64771 ----- Impact Factor: 9.625