Abstract :

Ripple-carry Adders Remain The Simplest Way To Build Wide Binary Adders, But Their Critical Path Grows Linearly With Word Width, Making Them A Persistent Bottleneck In Datapath-heavy VLSI Arithmetic. This Paper Presents A Modified Full-adder Cell That Exposes Its Internal Propagate Node, Already Computed On The Way To The Sum And Carry Outputs, As An Additional Output Port, An Introverted Design Choice That Reuses An Existing Internal Signal Externally Rather Than Recomputing An Equivalent One Outside The Cell. Four Such Cells Are Composed Into A 4-bit Carry-skip Block Whose Skip-enable Condition Is Built Directly From The Exposed Propagate Bits, And Four Blocks Form A 16-bit Carryskip Adder That Is Compared Against A Plain 16-bit Ripplecarry Adder Built From A Conventional Static-CMOS Full Adder. Both Designs Are Implemented And Post-place-androute Analyzed In Xilinx Vivado 2019.2 Targeting The Xc7a100tcsg324-1 Device Under A 10.0 Ns Timing Constraint. The Proposed Carry-skip Adder Reduces Critical-path Delay From 8.623 Ns To 7.402 Ns (14.2% Lower), Raises Throughput From 115.97 To 135.10 MOps/s (16.5% Higher), And Lowers Energy Per Operation From 724.332 PJ To 621.768 PJ (14.2% Lower), At The Cost Of 7 Additional LUTs (16 To 23, 43.8% More), With Power Tied At 0.084 W For Both Designs.

Published:

27-7-2026

Issue:

Vol. 26 No. 7 (2026)

Page Nos:

1310-1317

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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