Abstract :

Ternary Content-addressable Memory (TCAM) Is The Standard Building Block For Single-cycle Lookup In Networking, Packet Classification, And Associative Search, But Many SRAM-based Implementations Fall Back To A Sequential, RAM-style Comparator That Tests One Stored Entry Per Clock Cycle Rather Than Exploiting The Defining Parallel-search Property Of A True CAM, And Offer No Tolerance To SRAM Soft Errors. This Paper Presents And Compares Two 8-entry By 16-bit Ternary CAM Designs Targeting A Xilinx Artix-7 Device (xc7a100tcsg324-1, Vivado 2019.2). The Existing Design Is A Clocked Finite-state Machine That Advances Through The Eight-entry Table One Comparison Per Cycle, Requiring Up To Eight Cycles For An Exact-match Search. The Proposed Design Compares All Eight Entries Simultaneously In A Single Combinational Pass, Using A Per-entry Balanced-tree Mismatch Counter And A Boundedmismatch Match Rule That Declares A Match Whenever At Most One Bit Differs, Tolerating A Single-bit SRAM Soft Error That The Exact-match Design Cannot. Post-place-and-route Implementation Reports Under A 10.0 Ns Constraint Show The Proposed Architecture Reduces Worst-case Search Latency From 80.0 Ns (8 Cycles) To 6.015 Ns (one Pass) -- A 13.3x Reduction -- At A Cost Of 87.0% More Look-up Tables (43 Versus 23), With Power Consumption Tied At 0.084 W. The Results Demonstrate That Parallel Bounded-mismatch Matching Delivers Substantially Faster, Error-tolerant Search At A Modest And Well-understood Area Premium, An Attractive Trade For Latency-critical, Reliability-sensitive Lookup Applications.

Published:

27-7-2026

Issue:

Vol. 26 No. 7 (2026)

Page Nos:

1318-1327

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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