Abstract :

Fast Fourier Transform (FFT) Is A Key Building Block In Many Real-time Digital Signal Processing Systems. Hardware Implementation Of FFT Requires High Throughput, Low Latency, And Efficient Resource Utilization. This Paper Presents A Radix-2⁵ FFT Hardware Architecture Implemented Using A Multi-path Delay Commutator (MDC) Pipeline Structure. The Radix-2⁵ Algorithm Reduces The Number Of Computational Stages Compared To Conventional Radix-2 Architectures, While The MDC Pipeline Enables Parallel Data Processing For High Throughput. The Proposed Architecture Is Optimized To Reduce Hardware Complexity And Power Consumption By Efficient Use Of Butterfly Units And Twiddle Factor Multipliers. The Design Is Described Using Hardware Description Language And Evaluated In Terms Of Throughput, Latency, And Resource Utilization. Comparative Analysis Shows That The Proposed Radix-2⁵ MDC FFT Architecture Achieves Superior Performance Compared To Traditional Radix-2 And Radix-4 FFT Implementations, Making It Suitable For High-speed Real-time Applications.

Published:

29-7-2026

Issue:

Vol. 26 No. 7 (2026)

Page Nos:

1436-1441

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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