Abstract :

The Design Of Multiplier-Accumulator (MAC) Unit Can Be Implemented By Using The Vedic Multiplier Along With The Reversible Logic Gates. The Designing Of Vedic Multiplier Is Designed By Using The New Sutra Called “UrdhavaTriyagbhayam”. The Performance Of The MAC Operation Depends On The Multiplier Unit And The Adder Units. Here The Designing Of A Multiplier And An Adder Can Be Designed By Using The Reversible Gates To Get The High Speed Of Operation And Also A Vedic Multiplier Is Used For The Higher Performance, Lesser Area And To Reduce The Partial Products. Nowadays Reversible Computing Will Take A More Preferable For Low Power Dissipation, Higher Speed Of Operation. Here, We Proposed An 8, 16, 32, 64-bit Vedic Multiplier Is Designed By Using The RCA Based DKG Adder And Vedic Multiplier Is Designed By Using The CSLA Based DKG Adder Out Of These The Proposed DKG Gate Adder Based On CSLA Is Having The High Speed Of Operation. The Comparative Analysis Is Carried Out Among The Ripple Carry Adder (RCA), Carry Select Adder. Finally, It Has Been Proved That The Proposed CSLA Based DKG Gate With Vedic Multiplier- Adder Is Havingthe High Speed Of Operation. The Overall Simulation And Synthesis Process Is Carried Out With Xilinx ISE14.7 And Is Dumped On The FPGA Vertex7 Board.

Published:

14-8-2026

Issue:

Vol. 26 No. 8 (2026)

Page Nos:

925-936

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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