Abstract :

This Paper Presents The Design, Verification, And FPGA Implementation Of A Highperformance 64-bit Quad Serial Peripheral Interface (QSPI) Controller For High-speed Communication With External Flash Memory. The Proposed Architecture Incorporates A 64-bit Internal Data Path And Four-bit Parallel Data Transfer To Enhance Data-transfer Efficiency Over Conventional Single-bit SPI Communication. The Controller Is Developed In Verilog HDL And Employs A Finitestate-machine-based Control Architecture To Manage The Command, Address, Dummy, And Data Phases Of QSPI Transactions. Both Read And Write Operations Are Supported, With A 100 MHz System Clock And A 50 MHz QSPI Serial Clock. Functional Verification Is Performed Through RTL Simulation To Validate The Sequencing And Timing Of Control And Data Signals Across Different Transaction Phases. Following Verification, The Design Is Synthesized And Implemented On A Xilinx ZedBoard Featuring The Zynq-7000 XC7Z020 FPGA. Hardware Validation Confirms The Correct Operation Of The Chip-select, Serial Clock, And Quad I/O Signals During QSPI Read And Write Transactions. The Proposed Architecture Provides An Efficient FPGAbased Solution For High-speed Flash-memory Interfacing And Is Suitable For Data-intensive Embedded And Digital Systems Requiring Improved Transfer Efficiency And Reduced Transaction Latency.

Published:

28-9-2026

Issue:

Vol. 26 No. 9 (2026)

Page Nos:

476-484

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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