Abstract :

Flexible On-chip Interconnects Are Necessary Due To Increasing Complexity Of SoC As They Accommodate Different SoC Topologies. The AMBA AXI4 Protocol Is Prevalent Because Of Its Features Including Separate Read And Write Channels, Burst Transactions, Simultaneous Transactions, And Provision For Multiple Master-slaves. Unfortunately, There Are Significant Changes In RTL Required With Changes In Configuration Parameters Including Number Of Master/slaves, Address Size, And Data Size Among Others. In This Paper, An Automation Method And Scalable Framework Is Developed For Generating RTL For Configurable AMBA AXI4 Interconnects. The Architecture Parameters Can Be Configured Through A GUI Created Using Python. Thereafter, The Verilog RTL Will Be Automatically Generated Based On These Parameters Including AXI Channels, Arbitration, Address Decoding, Routing, And VALID/READY Handshaking. The Tool Is Evaluated Using Configurations Of 1M-2S, 2M-4S, 2M-8S, And 4M-8S In EDA Playground And EP Wave.

Published:

29-9-2026

Issue:

Vol. 26 No. 9 (2026)

Page Nos:

485-490

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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