Abstract :

Peripheral Component Interconnect Express (PCIe) Is A Layered And Serial Interconnect Protocol For Linking Processors, Memory, And Peripheral Devices, Contains The Transaction, Data Link, And Physical Layers. As PCIe IP Cores Advance Through Higher Generations (Gen1 Through Gen5) And Adopt Architectural Variants Such As Non-FLIT Mode, Ensuring That An Endpoint Implementation Correctly Interprets And Responds To The Full Range Of Transaction Layer Packets (TLPs) Becomes Increasingly Challenging. Existing Verification Approaches, Often Validate Only Nominal Transaction Flows, Leaving Gaps In Error Scenarios, Out-of-bound Transactions And Support Across Multiple Generations. This Work Addresses This Gap By Developing A Reusable UVM-based Verification Environment For Systematically Verifying PCIe Endpoint Functionality Across Gen1 Through Gen5. The Environment Is Built Around Two UVM Agents: An Active Agent, That Generates And Drives Memory, I/O, Configuration, And Message TLPs To The Endpoint Over A 256-bit AXI4 Interface, And A Passive Agent, Whose Monitor Observes And Captures Endpoint Responses Arriving Over The PCIe Lanes And The AXI Interface. Beyond Exercising Legal Transaction Sequences, The Environment Injects Errors In The TLPs To Verify That The Endpoint Behavior Conforms To The PCIe Specification. Functional Coverage Was Defined Across All Supported TLP Types To Quantitatively Assess Verification Completeness. The Environment Achieved 100% Functional Coverage Across All TLP Types, And Completion Status Received From The Endpoint. The Verification Environment Is Reusable Across PCIe Gen1 Through Gen5 Endpoint Designs, Offering A Scalable Foundation For Future Verification IP Development.

Published:

29-9-2026

Issue:

Vol. 26 No. 9 (2026)

Page Nos:

491-501

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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