Abstract :

The Increasing Demand For Higher Data Transfer Rates In Contemporary Computing Systems Has Significantly Increased The Complexity Of The PCI Express (PCIe) Protocol, Creating Substantial Challenges For Functional Verification And Debugging. This Paper Presents A UVM-based Verification Environment For PCIe Endpoint Validation, With An Enhanced Scoreboard As The Primary Component For Transaction-level Data Integrity And Protocol Compliance Verification. The Proposed Environment Models Communication Between A Root Port And An Endpoint Using PIPE-based Simulation And AXI-Stream Interfaces, Supporting Memory Read, Memory Write, Configuration Read/Write, And Programmed I/O Operations. A Protocol-aware Driver Generates Single- And Multi-beat TLP Transactions, While Link Training And Status State Machine (LTSSM) Monitoring Synchronizes Stimulus Generation With Valid Link States. The Proposed Scoreboard Maintains A Reference Model Using Shadow Memory To Track Data Written By Memory Write Transactions And Uses Tag-based Pending-request Tracking To Correlate Memory Read Requests With Their Corresponding Completion Responses. It Performs End-to-end Comparison Between Expected Data Maintained In The Reference Model And Actual Data Received From The Endpoint, Thereby Identifying Data Mismatches And Unexpected Responses. The Scoreboard Also Analyzes Completion Status And Detects Verification Conditions Including Unsupported Request (UR), Completer Abort (CA), Missing Or Orphaned Completions, Tag Reuse, And Other Transaction-level Protocol Violations. Structured Pass/fail Reporting And Transaction Tracking Provide Improved Visibility Into The Source Of Verification Failures And Reduce Dependence On Manual Waveform Analysis. Experimental Results Demonstrate That The Proposed Scoreboard-based Methodology Can Identify Transaction And Protocol Errors While Confirming Correct Data Integrity During Valid PCIe Operations. The Modular UVM Architecture Also Provides A Reusable Foundation For Extending Verification Toward Additional PCIe Features And Future Generations.

Published:

01-9-2026

Issue:

Vol. 26 No. 9 (2026)

Page Nos:

510-516

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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