Abstract :

This Paper Presents The Hardware Design Of A Power-efficient Bilateral Filter For Image Denoising On Field-Programmable Gate Arrays (FPGAs). An Approximate-computing Kernel Strategy Is Combined With A Novel Flip-flop-based Clock-gating Scheme To Substantially Reduce Dynamic Power While Preserving Denoising Quality. Spatial-domain And Intensity-range Kernel Coefficients Are Represented As Small Unsigned Integers, Removing Costly Exponential Evaluations And Multiplier-heavy Arithmetic. A D-flip-flop-synchronized AND-gated Clock Disables Register Toggling In The Filter Datapath Whenever A Valid Pixel Window Is Unavailable, Yielding A Glitch-free Gated Clock. Implemented On A Xilinx Zynq-7000 Device For A 5×5 Kernel And Verified With Xilinx Vivado And MATLAB 2020a, The Proposed Design Reduces Total On-chip Power By Approximately 51.3% (14.863 W → 7.238 W) And Slice-LUT Usage By 18.2% Relative To An Equivalent Design Without Clock Gating, At The Cost Of A 3.6% Increase In Critical-path Delay. PSNR And SSIM Quality Metrics Remain Within −4% And −14% Of An Accurate Software Bilateral Filter, Confirming That The Power Reduction Is Obtained Without Compromising Image Quality. The Results Support The Suitability Of The Proposed Methodology For Real-time, Energy-constrained Image-denoising Applications Envisioned Under Industry 5.0.

Published:

19-10-2026

Issue:

Vol. 26 No. 10 (2026)

Page Nos:

69-74

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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