Abstract :

As Semiconductor Technology Continues To Scale Toward Deep Sub-micron And Nanometer Nodes, Static Random Access Memory (SRAM) Design Faces Increasing Challenges Due To Short-channel Effects, Leakage Power, And Reduced Performance In Conventional CMOS Transistors. To Address These Limitations, This Work Presents The Design And Performance Evaluation Of A 14-transistor (14T) SRAM Cell Using FinFET Technology Incorporated With Modified LECTOR (LEakage Control TransistOR) And Dual Threshold Voltage (DVT) Techniques. These Approaches Aim To Significantly Minimize Leakage Power, Enhance Write/read Stability, And Improve Propagation Delay In Advanced Memory Architectures. The Proposed SRAM Cell Is Simulated Using HSPICE At 22 Nm Technology For 1-bit, 4-bit, And 8-bit Memory Configurations. Comparative Results With Conventional CMOSbased SRAM Show Substantial Improvement In Power Efficiency And Switching Performance. FinFET-based 14T SRAM Achieves Approximately 40–50% Lower Power Consumption With Reduced Dynamic Energy Dissipation And Faster Switching Characteristics. Further Analysis Highlights That FinFET-based Cells Offer Stronger Immunity To Leakage And Short-channel Effects, Making Them Highly Suitable For Low-voltage And High-speed Applications. The Design Demonstrates Excellent Scalability For Next-generation Cache Memory, IoT Edge Processors, Portable Electronic Devices, And Energy-efficient VLSI Systems. Keywords: SRAM, FinFET, Modified LECTOR, Dual Threshold Voltage (DVT), Low-Power VLSI, Leakage Reduction, Static Power Dissipation, HSPICE Simulation

Published:

11-12-2025

Issue:

Vol. 25 No. 12 (2025)

Page Nos:

181-190

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

How to Cite