Abstract :

Elliptic Curve Cryptography (ECC) Is A Widely Used Public-key Cryptographic Technique That Provides Strong Security With Relatively Smaller Key Sizes Than Conventional Algorithms Such As RSA. This Paper Presents The Design, RTL Verification, And FPGA Implementation Of An Optimized ECC Processor For Efficient Encryption And Decryption. The Proposed Architecture Incorporates Modular Arithmetic Units For Addition, Subtraction, Multiplication, And Inversion To Support Elliptic-curve Point Operations And Efficient Scalar Multiplication. The Design Is Developed Using Verilog HDL And Functionally Verified Through RTL Simulation And Waveform Analysis In Xilinx Vivado. The Verified Processor Is Implemented On A Zynq7000-based ZedBoard FPGA, Where ECC Encryption And Decryption Operations Are Executed On Hardware. On-chip Validation Is Performed Using Virtual Input/Output (VIO) And Integrated Logic Analyzer (ILA) For Hardware Control And Internal Signal Monitoring. The Implementation Is Evaluated In Terms Of Resource Utilization, Operating Frequency, Latency, And Power Consumption, Demonstrating The Practical Feasibility Of Optimized ECC Hardware.

Published:

28-9-2026

Issue:

Vol. 26 No. 9 (2026)

Page Nos:

468-475

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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