Abstract :

Memory Controllers In Safety-critical System-on-Chip (SoC) Platforms Must Stay Dependable Even When Stored Bits Are Disturbed By Radiation Or Electrical Noise. This Paper Describes The Design And Functional Verification Of A Soft-errorresilient SRAM Controller That Exposes An AMBA AXI4-Lite Slave Port. Where Earlier Parameterizable Controllers Concentrate On Flexibility And Burst Throughput, The Present Design Adds A Single Error Correction, Double Error Detection (SECDED) Block Based On The Hamming Code, So That A Corrupted Word Can Be Repaired Before It Reaches The Bus Master. The Controller Is Written In SystemVerilog And Exercised With A Universal Verification Methodology (UVM) Testbench Whose Randomized Fault-injection Sequence Flips Memory Bits On Demand. Synthesis And Implementation In Vivado For The Xilinx Zynq-7000 Device (xc7z020) Report 188 Slice LUTs, 120 Slice Registers And 0.117 W Of Total On-chip Power. Compared With A Reference AXI4-Full Reconfigurable Controller (395 LUTs, 1.395 W), This Is About 52% Fewer LUTs And A 91.6% Lower Reported Power Figure. Simulation Shows That Every Injected Single-bit Error Is Corrected And That Double-bit Errors Raise An Error Flag, Which Makes The Controller A Suitable Memory IP Block For Automotive And Other Safety-critical SoCs. Keywords— AXI4-Lite, SRAM Controller, SECDED ECC, Hamming Code, Soft Errors, Fault Injection, UVM, Zynq-7000, Low-power VLSI.

Published:

02-11-2026

Issue:

Vol. 26 No. 11 (2026)

Page Nos:

61-65

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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